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AD9022 rev. b a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 12-bit 20 msps monolithic a/d converter product description the AD9022 is a high speed, high performance, monolithic 12-bit analog-to-digital converter. all necessary functions, in- cluding track-and-hold (t/h) and reference, are included on-chip to provide a complete con version solution. it is a companion unit to the ad9023; the primary difference between the two is that all logic for the AD9022 is ttl-compatible, while the ad9023 utilizes ecl logic for digital inputs and out- puts. pinouts for the two parts are nearly identical. operating from +5 v and C5.2 v supplies, the AD9022 pro- vides excellent dynamic performance. sampling at 20 msps with a in = 1 mhz, the spurious-free dynamic range (sfdr) is typically 76 db; with a in = 9.6 mhz, sfdr is 74 db. snr is typically 65 db. the onboard t/h has a 110 mhz bandwidth and, more impor- tantly, is designed to provide excellent dynamic performance for analog input frequencies above nyquist. this feature is neces- sary in many undersampling signal processing applications, such as in direct if-to-digital conversion. to maintain dynamic performance at higher ifs, monolithic rf track-and-holds (such as the ad9100 and ad9101 samplifier?) can be used with the AD9022 to process signals up to and beyond 70 mhz. with dnl typically less than 0.5 lsb and 20 ns transient re- sponse settling time, the AD9022 provides excellent results when low-frequency analog inputs must be oversampled (such as ccd digitization). the full scale analog input is 1 v with a 300 w input impedance. the analog input can be driven directly from the signal source, or can be buffered by the ad96xx series of low noise, low distortion buffer amplifiers. all timing is internal to the AD9022; the clock signal initiates the conversion cycle. for best results, the encode command should contain as little jitter as possible. high speed layout practices must be followed to ensure optimum a/d perfor- mance. the AD9022 is built on a trench isolated bipolar process and utilizes an innovative multipass architecture (see the block diagram). the unit is packaged in 28-lead ceramic dips and gullwing surface mount packages. the AD9022 is specified to operate over the industrial (C25 c to +85 c) and military (C55 c to +125 c) temperature ranges. functional block diagram 4-bit adc 5-bit adc digital error correction 12 ttl +2v ref gnd +5v C5.2v encode analog input AD9022 t/h 5-bit adc dac dac t/h 16 8 features monolithic 12-bit 20 msps a/d converter low power dissipation: 1.4 watts on-chip t/h and reference high spurious-free dynamic range ttl logic applications radar receivers digital communications digital instrumentation electro-optics one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 samplifier is a trademark of analog devices, inc.
AD9022Cspecifications electrical characteristics test AD9022aq/az AD9022bq/bz AD9022sq/sz parameter (conditions) temp level min typ max min typ max min typ max units resolution 12 12 12 bits dc accuracy differential nonlinearity +25 c i 0.6 0.75 0.4 0.5 0.6 0.75 lsb full vi 1.0 1.0 1.0 lsb integral nonlinearity +25 c i 1.3 2.5 1.3 2.0 1.3 2.5 lsb full vi 1.6 3.0 1.6 3.0 1.6 3.0 lsb no missing codes full vi guaranteed guaranteed guaranteed offset error +25 ci 525 525 525 mv full vi 15 35 15 35 15 35 mv gain error +25 c i 0.5 2.5 0.5 2.5 0.5 2.5 % fs full vi 0.6 3.5 0.6 3.5 0.6 3.5 % fs thermal noise +25 c v 0.57 0.57 0.57 lsb, rms analog input input voltage range 1.024 1.024 1.024 v input resistance full iv 240 300 360 240 300 360 240 300 360 w input capacitance +25 cv 5 5 5 pf analog bandwidth +25 c v 110 110 110 mhz switching performance 1 minimum conversion rate +25 c iv 4 4 4 msps maximum conversion rate full vi 20 20 20 msps aperture delay (t a ) +25 c iv 0.55 0.71 0.85 0.55 0.71 0.85 0.55 0.71 0.85 ns aperture uncertainty (jitter) +25 c v 6 6 6 ps, rms output delay (t od ) full vi 15 27.5 15 27.5 15 27.5 ns encode input logic compatibility ttl ttl ttl logic 1 voltage full vi 2.0 2.0 2.0 v logic 0 voltage full vi 0.8 0.8 0.8 v logic 1 current full vi 8 20 8 20 8 20 m a logic 0 current full vi 8 20 8 20 8 20 m a input capacitance +25 cv 6 6 6 pf pulsewidth (high) +25 c iv 22.5 125 22.5 125 22.5 125 ns pulsewidth (low) +25 c iv 20 125 20 125 20 125 ns dynamic performance transient response +25 c v 20 20 20 ns overvoltage recovery time +25 c v 20 20 20 ns harmonic distortion analog input @ 1.2 mhz +25 c i 65 73 70 75 65 73 dbc @ 1.2 mhz full v 70 72 70 dbc @ 4.3 mhz +25 c v 73 75 73 dbc @ 9.6 mhz +25 c i 63 72 69 74 63 72 dbc @ 9.6 mhz full v 68 72 68 dbc signal-to-noise ratio 2 analog input @ 1.2 mhz +25 c i 62 64 64 66 62 64 db @ 1.2 mhz full v 63 65 63 db @ 4.3 mhz +25 c v 64 66 64 db @ 9.6 mhz +25 c i 61 63 63 65 61 63 db @ 9.6 mhz full v 62 63 62 db signal-to-noise ratio 2 (without harmonics) analog input @ 1.2 mhz +25 c i 63 66 65 67 63 66 db @ 1.2 mhz full v 64 66 64 db @ 4.3 mhz +25 c v 66 66 66 db @ 9.6 mhz +25 c i 62 65 64 66 62 65 db @ 9.6 mhz full v 63 65 63 db (+v s = +5 v; Cv s = C5.2 v; encode = 20 msps, unless otherwise noted) C2C rev. b
C3C ordering guide temperature package package model range description option AD9022aq/bq C25 c to +85 c 28-lead ceramic dip q-28 AD9022az/bz C25 c to +85 c 28-pin ceramic z-28 leaded chip carrier AD9022sq C55 c to +125 c 28-lead ceramic dip q-28 AD9022sz C55 c to +125 c 28-pin ceramic z-28 leaded chip carrier n C 2 n C 1 data output n n C 3 n n + 1 analog in t od = 15C27.5 typical n + 2 t od encode t a t a = 0.7 typical AD9022 timing diagram absolute maximum ratings 1 +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v Cv s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C6 v analog input . . . . . . . . . . . . . . . . . . . . . . . . . C1.5 v to +1.5 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v s to 0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature range AD9022aq/az/bq/bz . . . . . . . . . . . . . . . C25 c to +85 c AD9022sq/sz . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c maximum junction temperature 2 . . . . . . . . . . . . . . . . +175 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c storage temperature range . . . . . . . . . . . . C65 c to +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances: q package (ceramic dip): q jc = 10 c/w; q ja = 35 c/w. z package (gullwing surface mount): q jc = 13 c/w; q ja = 45 c/w. AD9022 test AD9022aq/az AD9022bq/bz AD9022sq/sz parameter (conditions) temp level min typ max min typ max min typ max units two-tone intermodulation distortion rejection 3 +25 c v 74 74 74 dbc digital outputs 1 logic compatibility ttl ttl ttl logic 1 voltage full vi 2.4 2.4 2.4 v logic 0 voltage full vi 0.5 0.5 0.5 v output coding offset binary offset binary offset binary power supply +v s supply voltage full vi 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 ma +v s supply current full vi 100 120 100 120 100 120 ma Cv s supply voltage full vi C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 ma Cv s supply current full vi 180 220 180 220 180 220 ma power dissipation full vi 1.4 1.9 1.4 1.9 1.4 1.9 w power supply rejection ratio (psrr) 4 full v 32 32 32 mv/v notes 1 AD9022 load is a single ls latch. 2 rms signal-to-rms noise with analog input signal 1 db below full scale at specified frequency. tested at 55% duty cycle. 3 intermodulation measured with analog input frequencies of 8.9 mhz and 9.8 mhz at 7 db below full scale. 4 psrr is sensitivity of offset error to power supply variations within the 5% limits shown. specifications subject to change without notice. rev. b
C4C AD9022 rev. b explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for extended temperature devices; guaranteed by design and character- ization testing for industrial devices. die layout and mechanical information die dimensions . . . . . . . . . . . . . . . . 205 228 21 ( 1) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080 passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride bond wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum pin function descriptions pin no. name function 1C3 d3Cd1 digital output bits of adc; ttl compatible. 4 d0 (lsb) least significant bit of adc output; ttl compatible. 5 nc no connection internally 6+v s +5 v power supply 7 gnd ground 8 encode encode clock input to adc. internal t/h is placed in hold mode (adc is encoding) on rising edge of encode signal. 9 gnd ground 10 +v s +5 v power supply 11 gnd ground 12 a in noninverting input to t/h amplifier. 13 Cv s C5.2 v power supply 14 +v s +5 v power supply 15 Cv s C5.2 v power supply 16 gnd ground 17 comp should be connected to Cv s through 0.1 m f capacitor. 18 d11 (msb) most significant bit of adc output; ttl compatible. 19C25 d10Cd4 digital output bits of adc; ttl compatible. 26 +v s +5 v power supply 27 Cv s C5.2 v power supply 28 gnd ground pin designations top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD9022 nc = no connect compensation (pin 17) should be connected to Cv s through 0.01 m f +v s Cv s a in gnd +v s gnd encode d3 d2 d1 d0 (lsb) gnd +v s nc Cv s gnd comp d11(msb) d10 d9 d8 gnd Cv s +v s d4 d7 d6 d5
AD9022 rev. b C5C definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. aperture delay the delay between the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. harmonic distortion the rms value of the fundamental divided by the rms value of the worst harmonic component. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line de- termined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency tested drops by no more than 3 db below the guaran- teed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% point of the rising edge of the en- code command and the time when all output data bits are within valid logic levels. overvoltage recovery time the amount of time required for the converter to recover to 12-bit accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise ratio (snr) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral compo- nents, including harmonics but excluding dc, with an analog input signal 1 db below full scale. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral compo- nents, excluding the first five harmonics and dc, with an analog input signal 1 db below full scale. transient response the time required for the converter to achieve 12-bit accuracy when a step function is applied to the analog input. two-tone intermodulation distortion (imd) rejection the ratio of the power of either of two input signals to the power of the strongest third-order imd signal. analog input Cv s +v s +v s 180 v 120 v 10pf encode input 11k v 12k v Cv s digital output +v s analog input out p ut sta g e Cv s 100 v 900 v +v s encode compensation 20pf 50 v compensation Cv s Cv s figure 1. equivalent circuits
C6C AD9022 rev. b Ctypical performance characteristics analog input frequency C mhz C76 C72 C68 010 1 worst case harmonic distortion C dbc 23456789 C75 C74 C70 C69 C73 C71 +25 8 c room C55 8 c +125 8 c figure 2. harmonic distortion vs. analog input frequency encode rate C msps 85 harmonics and snr C db 5.0 worst harmonics snr a in = 1.2mhz 80 75 70 65 60 55 7.5 10.0 12.5 17.5 15.0 20.0 22.5 25.0 figure 3. snr and harmonics vs. encode rate differential nonlinearity C lsbs output code 2.0 C2.0 4096 C1.0 C1.5 1024 0 C0.5 0.5 1.0 1.5 3072 2048 a in = 1.2mhz f s = 20msps figure 4. differential nonlinearity vs. output code 70 35 19.3 50 40 2.3 45 1.24 65 55 60 17.3 15.3 13.3 9.6 7.3 5.3 11.3 analog input frequency C mhz snr C db +25 8 c C55 8 c +125 8 c figure 5. signal-to-noise ratio vs. analog input frequency 90 0 C1 20 10 C45 C50 30 40 50 60 70 80 C5 C10 C15 C20 C25 C30 C35 C40 sfdr and snr C db input level C db a in = 1.2mhz encode = 20mhz sfdr snr figure 6. sfdr and snr vs. analog input level 0 C1 20 10 C45 C50 30 40 50 60 70 80 C5 C10 C15 C20 C25 C30 C35 C40 sfdr and snr C db input level C db a in = 9.6mhz encode = 20mhz sfdr snr figure 7. sfdr and snr vs. analog input level
AD9022 rev. b C7C is present when the unit is strobed with an encode com- mand. the conversion process begins on the rising edge of this pulse, which should conform to the minimum and maximum pulsewidth requirements shown in the specifications. operation below the recommended encode rate (4 msps) may result in excessive droop in the internal t/h devicesCleading to large dc and ac errors. the held analog value of the first track-and-hold is applied to a 5-bit flash converter and a second t/h. the 5-bit flash con- verter resolves the most significant bits (msbs) of the held analog voltage. these five bits are reconstructed via a 5-bit dac and subtracted from the original t/h output signal to form a residue signal. a second t/h holds the amplified residue signal while it is en- coded with a second 5-bit flash adc. again the five bits are reconstructed and subtracted from the second t/h output to form a residue signal. this residue is amplified and encoded with a 4-bit flash adc to provide the three least significant bits (lsbs) of the digital output and one bit of error correction. digital error correction logic aligns the data from the three flash converters and presents the result as a 12-bit parallel digi- tal word. the output stage of the AD9022 is ttl. output data may be strobed on the rising edge of the encode command. AD9022 in receiver applications advances in semiconductor processes have resulted in low cost digital signal processing (dsp) and analog signal processing which can help create cost effective alternative receiver designs. today, an all-digital receiver allows tuning, demodulation, and detection of receiver signals in the digital domain. by digitizing if signals directly, and utilizing digital techniques, it becomes possible to make significant improvements in receiver design. for high frequency ifs, the adc is the key to the receivers performance. unfortunately, the specifications frequently used by receiver designers and analog-to-digital (adc) manufactur- ers are often very different. noise figure and intercept point are common measures of noise and linearity in analog rf system design. adcs are more frequently specified in terms of snr and harmonic distortion. noise noise figure (nf) is a measure of receiver sensitivity and is defined as the degradation of signal-to-noise ratio (snr) as a signal passes through a device. in equation form: nf = snr ( in ) C snr ( out ) noise figure is a bandwidth invariant parameter for reasonably narrow bandwidths in most devices. the system noise figure for a combination of amplifiers and mixers, for instance, can be analyzed without regard to the information bandwidth. thermal noise contribution from the adc behaves in a similar fashion; however, the spectral density of quantization noise is a function of the sample rate. in addition, the spectral density of the quantization noise is flat only in an adc with perfect linear- ity, i.e., perfect 1 lsb step sizes. to analyze the system noise performance, adc noise figure is calculated by normalizing the snr of the adc output to a 1 hz bandwidth. this result is given by: snr (/ hz ) = snr + 10 log 10 ( f s /2) where f s is the sample rate. theory of operation refer to the block diagram. the AD9022 employs a three-pass subranging architecture and digital error correction. this combination of design techniques ensures 12-bit accuracy at relatively low power. analog input signals are immediately attenuated through a resistor divider and applied directly to the sampling bridge of the track-and-hold (t/h). the t/h holds whatever analog value 0 C100 C70 C90 C80 C40 C60 C50 C30 C20 C10 full scale C db frequency C mhz 10 0 a in = 1.2mhz a in = C1.0dbfs snr = 66.7db thd = 77.51db sfdr = 79.49dbfs figure 8. fft plot 0 C100 C70 C90 C80 C40 C60 C50 C30 C20 C10 full scale C db frequency C mhz 10 a in = 9.6mhz a in = C1.0dbfs snr = 66.05db thd = 74.28db sfdr = 75.32dbfs 0 figure 9. fft plot 10.0 0.0 8.0 6.0 4.0 2.0 a in1 = 8.9mhz a in2 = 9.8mhz a in1 = 7.0dbfs a in2 = 7.0dbfs sfdr = 80.62dbfs 0 100 80 40 60 20 full scale C db fre q uency C mhz 120 figure 10. two-tone fft
C8C AD9022 rev. b this will be true only for converters in which perfect quantiza- tion noise dominates. there may be an upper sample rate, above which the thermal noise of the converter is the dominant source of noise. in this case, normalization would be based on the noise bandwidth of the adc. for an AD9022 with a typical snr of 64 db and a sample rate of 20 msps, the normalized snr is equal to 134 db (64 + 70). both thermal and quantiza- tion noise contribute to this number. the snr of the input is assumed to be limited by the thermal noise of the input resistance, or C174 dbm/hz. the input signal level is +10 dbm (2 v p-p into 50 w ). noise figure of the adc can be calculated by: nf = snr ( in ) C snr ( out ) = [+10 C (174)] C 134 = 50 db most adcs detect input voltage levels, not power. conse- quently, the input snr can be determined more accurately by determining the ratio of the signal voltage to the noise voltage of the terminating resistor. however, both the input signal and noise voltage delivered to the adc are also a function of the source impedance. the dependence of nf on sample rate, linearity, source and terminating impedances, and the number of assumptions required, highlight the weakness of using nf as a figure of merit for an adc. the rather large number that results bolsters this belief by indicating the adc is often the weakest link in the signal processing path. linearity the third order intercept point for a linear device (with some nonlinearity) is a good way to predict 3rd order spurious signals as a function of input signal level. for an adc, however, this in an invalid concept except with signals near full scale. as the input signal is reduced, the performance burden shifts from the input track-and-hold (t/h) to the encoder. this creates a non- linear function, as contrasted with the third order intercept behavior, which predicts an improvement in dynamic range as the signal level is decreased. for signals near full scale, the intercept point is calculated the same as any device: intercept point = [ harmonic suppression /( n C1)] + input power where n = the order of the imd (3 in this case) ad 9022 intercept point = 80/2 + 3 dbm (7 dbm below full scale ) = 43 dbm for signals below this level, the spurious free dynamic range (sfdr) curves shown in the data sheet are a more accurate predictor of dynamic range. the sfdr curve is generated by measuring the ratio of the signal (either tone in the two-tone measurement) to the worst spurious signal, which is observed as the analog input signal amplitude is swept. the worst spurious signal is usually the second harmonic or 3rd order imd. actual results are shown on several plots. the straightline with a slope of one is constructed at the point where the worst sfdr touches the line. this line, extrapolated to full scale, gives the sfdr of the adc. this value can then be used to predict the dynamic range by simply subtracting the input level from the sfdr. it should be noted that all sfdr lines are constructed to be valid only below a certain level below full scale. above these points, the linearity of the device is dominated by the nonlineari ties of the front end and best predicted by the intercept point. AD9022 noise performance high speed, wide bandwidth adcs such as the AD9022 are optimized for dynamic performance over a wide range of analog input frequencies. however, there are many applications (imag- ing, instrumentation, etc.) where dc precision is also important. due to the wide input bandwidth of the AD9022 for a given input voltage, there will be a range of output codes which may occur. this is caused by unavoidable circuit noise within the wideband circuits in the adc. if a dc signal is applied to the adc and several thousand outputs are recorded, a distribution of codes such as that shown in the histogram below may result. relative frequency of occurrence output code 2.0 C2.0 C1.0 C1.5 xC3 0 C0.5 0.5 1.0 1.5 one standard deviation = rms noise level xC2 xC1 x x+1 x+2 x+3 figure 11. adc equivalent input noise the correct code appears most of the time, but adjacent codes also appear with reduced probability. if a normal probability density curve is fitted to this gaussian distribution of codes, the standard deviation will be equal to the equivalent input rms noise of the adc. the rms noise may also be approximated by converting the snr, as measured by a low frequency fft, to an equivalent input noise. this method is accurate only if the snr performance is dominated by random thermal noise (the low frequency snr without harmonics is the best measure). sixty-three db equates to 1 lsb rms for a 2 v p-p (0.707 v rms) input signal. the AD9022 has approximately 0.5 lsb of rms noise or a noise limited snr of 69 db, indicating that noise alone does not limit the snr performance of the device (quanti- zation noise and linearity are also major contributors). this thermal noise may come from several sources. the drive source impedance should be kept low to minimize resistor thermal noise. some of the internal adc noise is generated in the wideband t/h. sampling adcs generally have input band- widths which exceed the nyquist frequency of one-half the sampling rate. (the AD9022 has an input bandwidth of over 100 mhz, even though the sampling rate is limited to 20 msps.) wide bandwidth is required to minimize gain and phase distor- tion and to permit adequate settling times in the internal ampli- fiers and t/hs. but a certain amount of unavoidable noise is generated in the t/h and other wideband circuits within the adc; this causes variation in output codes for dc inputs. good layout, grounding and decoupling techniques are essential to prevent external noise from coupling into the adc and further corrupting performance.
AD9022 rev. b C9C using the AD9022 layout information preserving the accuracy and dynamic performance of the AD9022 requires that designers pay special attention to the layout of the printed circuit board. analog paths should be kept as short as possible and be properly terminated to avoid reflections. the analog input connection should be kept away from digital signal paths; this reduces the amount of digital switching noise, which is capacitively coupled into the analog section. digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. the AD9022 digital outputs should be buff- ered or latched close to the device (<2 cm). this prevents load transients that may feed back into the device. in high speed circuits, layout of the ground is critical. a single, low impedance ground plane on the component side of the board is recommended. power supplies should be capacitively coupled to the ground plane with high quality 0.1 m f chip ca- pacitors to reduce noise in the circuit. all power pins of the AD9022 should be bypassed individually. the compensation pin (comp pin 17) should be bypassed directly to the Cv s supply (pin 15) as close to the part as possible using a 0.1 m f chip capacitor. multilayer boards allow designers to lay out signal traces with- out interrupting the ground plane, and provide low impedance ground planes. in systems with dedicated analog and digital grounds, all grounds for the AD9022 should be connected to the analog ground plane. in systems using multilayer boards, dedicated power planes are recommended to provide low impedance connections for device power. sockets limit dynamic performance and are not recom- mended for use with the AD9022. timing conversion by the AD9022 is initiated by the rising edge of the encode clock (pin 8). all required timing is generated inter- nal to the adc. care should be taken to ensure that the encode clock to the AD9022 is free from jitter that can degrade dy- namic performance. the clock driver should be compatible with ttl ls logic series devices. drivers with excessive slew rate or overdrive will degrade the dynamic performance of the AD9022. pulsewidth of the adc encode clock must be controlled to ensure the best possible performance. dynamic performance is guaranteed with a clock pulse high minimum of 25 ns. opera- tion with narrower pulses will degrade snr and dynamic per- formance. from a system perspective, this is generally not a problem, because a simple inverter can be used to generate a suitable clock if the system clock is less than 25 ns wide. the AD9022 provides latched data outputs. data outputs are available two pipeline delays and one propagation delay after the rising edge of the encode clock (refer to the AD9022 timing diagram). the length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9022; these transients can detract from the converters dynamic performance. operation at encode rates less than 4 msps is not recom- mended. the internal track-and-hold saturates, causing errone- ous conversions. this t/h saturation precludes clocking the AD9022 in a burst mode. the duty cycle of the encode clock for the AD9022 is critical for obtaining rated performance of the adc. internal pulsewidths within the track-and-hold are established by the encode com- mand pulsewidth; to ensure rated performance, minimum and maximum pulsewidth restrictions should be observed. operation at 20 msps is optimized when the duty cycle is held at 55%. analog input the analog input (pin 12) voltage range is nominally 1.024 volts. the range is set with an internal voltage reference and cannot be adjusted by the user. the input resistance is 300 w and the analog bandwidth is 110 mhz, making the AD9022 useful in undersampling applications. the AD9022 should be driven from a low impedance source. the noise and distortion of the amplifier should be considered to preserve the dynamic range of the AD9022. power supplies the power supplies of the AD9022 should be isolated from the supplies used for noisy devices (digital logic especially) to re- duce the amount of noise coupled into the adc. for optimum performance, linear supplies ensure that switching noise from the supplies does not introduce distortion products during the encoding process. if switching supplies must be used, decoupling recommendations above are critically important. the psrr of the AD9022 is a function of the ripple frequency present on the supplies. clearly, power supplies with the lowest possible frequency should be selected. AD9022 evaluation board the evaluation board for the AD9022 (AD9022/pcb) provides an easy and flexible method for evaluating the adcs perfor- mance without (or prior to) developing a user-specific printed circuit board. the two-sided board includes a reconstruction dac and digital output interface, and uses the layout and appli- cations suggestions outlined above. it is available at nominal cost from analog devices, inc. input/output/supply information power supply, analog input, clock connections and recon- structed output (rc output) are identified by labels on the evaluation board. operation of the evaluation board will conform to the following characteristics: parameter typical units supply current +5 v 150 ma C5 v 300 ma a in impedance 51 w voltage range 1.024 v clock impedance 51 w frequency 20 msps rc output impedance 51 w voltage range 0 to C1 v
C10C AD9022 rev. b analog input analog input signals can be directly fed into the device under test input (a in ). the a in input is terminated at the device with a 62 w resistor to give a parallel equivalent of 51 w (62 w i 300 w ). dac reconstruction the AD9022 evaluation board provides an onboard ad9713b reconstruction dac for observing the digitized analog input signal. the ad9713b is terminated into 51 w to provide a 1 v p-p signal at the output (rc output). output data the output data bits are latched with two 74ls574 latches which drive a 40-pin connector (amp p/n 102153-09). the data and clock signals are available at the connector per the pin assignments shown on the schematic of the evaluation board. data is latched on the rising edge of the encode clock. 8 12 1d 2d 3d 4d 5d 6d 7d 8d 1q 2q 3q 4q 5q 6q 7q 8q ck oe u4 74ls574 2 3 4 5 6 7 8 9 25 24 23 22 21 20 19 18 17 d9 d10 d11 d12 lsb encode a in d8 d7 d6 d5 d4 d3 d2 msb d1 comp u1 AD9022q C5.2v c4 0.1 m f 11 1 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 10 11 14 28 r12 r14 r15 r16 r17 r18 r19 r20 d12 (lsb) d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 (msb) le 26 r8 r9 r10 r11 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 20 19 C5.2v r4 7.5k v c5 0.1 m f r5 51 v rc out u2 ad9698r 14 13 16 3 4 u2 ad9698r 11 12 9 6 5 r1 51 v +5v 1 2 cr1 ad589h c1 0.1 m f bnc j1 clock r7 62 v a in e2 e1 bnc j2 u5 ad9713p r6 51 v bnc j4 clk r2 5.1k v r21 100 v u6 74as32 8 9 10 rset refout cin cout refin iout 24 18 r3 20 v 17 16 14 iout 1d 2d 3d 4d 5d 6d 7d 8d 1q 2q 3q 4q 5q 6q 7q 8q ck oe u3 74ls574 2 3 4 5 6 7 8 9 11 1 19 18 17 16 15 14 13 12 c13 0.1 m f c2 10 m f 20% 35v c6 0.1 m f c7 0.1 m f c8 0.1 m f c9 0.1 m f c10 0.1 m f c11 0.1 m f c12 0.1 m f +5v c22 0.1 m f u6 74as32 3 1 2 u6 74as32 6 4 5 u6 74as32 11 13 12 clk d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 h40dmc j3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j5 C5.2v j6 +5v j7 gnd c3 10 m f 20% 35v c14 0.1 m f c15 0.1 m f c16 0.1 m f c17 0.1 m f c18 0.1 m f c19 0.1 m f c20 0.1 m f c21 0.1 m f C5.2v figure 12. AD9022/pcb evaluation board schematic
AD9022 rev. b C11C figure 13. top of board, viewed from top figure 14. center of board, viewed from top
C12C AD9022 rev. b printed in u.s.a. c1964aC0C1/98 figure 15. bottom of board, viewed from bottom 28-lead cerdip (q-28) 28 114 15 0.610 (15.49) 0.500 (12.70) pin 1 0.005 (0.13) min 0.100 (2.54) max 15 0 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225 (5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) outline dimensions dimensions shown in inches and (mm). 28-pin ceramic leaded chip carrier (z-28) top view 114 15 0.050 (1.27) typ 28 0.015 (0.381) min 0.73 (18.544) 0.71 (18.036) 0.51 (12.954) 0.49 (12.446) 0.025 (0.635) min 0.115 (2.921) max 0.060 (1.524) 0.040 (1.016) 0.165 (4.191) max 0.012 (0.305) 0.009 (0.229) 0.765 (19.431) 0.745 (18.923)

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